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74HC132 Quad 2-Input NAND Gate with Schmitt-Trigger Inputs
High-Performance Silicon-Gate CMOS
The 74HC132 is identical in pinout to the LS132. The device inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs. The HC132 can be used to enhance noise immunity or to square up slowly changing waveforms.
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MARKING DIAGRAMS
14 SOIC-14 D SUFFIX CASE 751A 1 HC132G AWLYWW
* * * * * * * * *
Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements as Defined by JEDEC Standard No. 7A ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 72 FETs or 18 Equivalent Gates These are Pb-Free Devices
14 TSSOP-14 DT SUFFIX CASE 948G 1 HC 132 ALYW G G
A1 B1 Y1 A2 B2 Y2 GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC B4 A4 Y4 B3 A3 Y3
HC132 = Device Code A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
FUNCTION TABLE
Inputs A L L H H B L H L H Output Y H H H L
Figure 1. Pin Assignment
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2007
March, 2007 - Rev. 1
1
Publication Order Number: 74HC132/D
74HC132
A1
1 3 Y1
B1 A2
2 4 6 Y2
B2 A3
5 9 8 Y = AB
Y3
B3
10
A4 12 11 B4 13 PIN 14 = VCC PIN 7 = GND Y4
Figure 2. Logic Diagram
ORDERING INFORMATION
Device 74HC132DR2G 74HC132DTR2G Package SOIC-14 (Pb-Free) TSSOP-14* Shipping 2500 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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74HC132
MAXIMUM RATINGS
Symbol VCC VIN VOUT IIK IOK IOUT ICC IGND TSTG TL TJ qJA PD MSL FR VESD ILatchup Positive DC Supply Voltage Digital Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance Power Dissipation in Still Air at 85_C Moisture Sensitivity Flammability Rating ESD Withstand Voltage Latchup Performance Oxygen Index: 30% - 35% Human Body Model (Note 1) Machine Model (Note 2) Above VCC and Below GND at 85_C (Note 3) 14-SOIC 14-TSSOP SOIC TSSOP Output in 3-State High or Low State Parameter Value *0.5 to )7.0 *0.5 to )7.0 *0.5 to )7.0 *0.5 to VCC )0.5 *20 $20 $25 $75 $75 *65 to )150 260 )150 125 170 500 450 Level 1 UL 94 V-0 @ 0.125 in u2000 u200 $300 V mA Unit V V V mA mA mA mA mA _C _C _C _C/W mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA/JESD22-A114-A. 2. Tested to EIA/JESD22-A115-A. 3. Tested to EIA/JESD78. 4. For high frequency or heavy load considerations, see Chapter 2the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 3) Min 2.0 0 *55 - Max 6.0 VCC )125 No Limit (Note 5) Unit V V _C ns
5. When VIN X 0.5 VCC, ICC >> quiescent current. 6. Unused inputs may not be left open. All inputs must be tied to a high-logic voltage level or a low-logic input voltage level.
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74HC132
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VT+max Parameter Maximum Positive-Going Input Threshold Voltage (Figure 5) Minimum Positive-Going Input Threshold Voltage (Figure 5) Maximum Negative-Going Input Threshold Voltage (Figure 5) Minimum Negative-Going Input Threshold Voltage (Figure 5) Maximum Hysteresis Voltage (Figure 5) Minimum Hysteresis Voltage (Figure 5) Minimum High-Level Output Voltage Test Conditions VOUT = 0.1 V |IOUT| v 20 mA VOUT = 0.1 V |IOUT| v 20 mA VOUT = VCC - 0.1 V |IOUT| v 20 mA VOUT = VCC - 0.1 V |IOUT| v 20 mA VOUT = 0.1 V or VCC - 0.1 V |IOUT| v 20 mA VOUT = 0.1 V or VCC - 0.1 V |IOUT| v 20 mA VIN v VT-min or VT+max |IOUT| v 20 mA VIN v -VT-min or VT+max |IOUT| v 4.0 mA |IOUT| v 5.2 mA (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 |IOUT| v 4.0 mA |IOUT| v 5.2 mA 4.5 6.0 6.0 6.0 1.5 3.15 4.2 1.0 2.3 3.0 0.9 2.0 2.6 0.3 0.9 1.2 1.2 2.25 3.0 0.2 0.4 0.5 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 $0.1 2.0 Guaranteed Limit *55_C to 25_C v85_C 1.5 3.15 4.2 0.95 2.25 2.95 0.95 2.05 2.65 0.3 0.9 1.2 1.2 2.25 3.0 0.2 0.4 0.5 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 $1.0 20 v125_C 1.5 3.15 4.2 0.95 2.25 2.95 0.95 2.05 2.65 0.3 0.9 1.2 1.2 2.25 3.0 0.2 0.4 0.5 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 $1.0 40 mA mA V Unit V
VT+min
V
VT-max
V
VT-min
V
VHmax (Note 7) VHmin (Note 7) VOH
V
V
V
VOL
Maximum Low-Level Output Voltage
VIN VT+max |IOUT| v 20 mA VIN VT+max
IIN ICC
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
VIN = VCC or GND VIN = VCC or GND IOUT = 0 mA
7. VHmin u (VT+min) * (VT-max); VHmax = (VT+max) ) (VT-min). 8. Information on typical parametric values can be found in the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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74HC132
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
VCC Symbol tPLH, tPHL tTLH, tTHL Cin Parameter Maximum Propagation Delay, Input A or B to Output Y (Figures 3 and 4) Maximum Output Transition Time, Any Output (Figures 3 and 4) Maximum Input Capacitance (V) 2.0 4.5 6.0 2.0 4.5 6.0 -- 125 25 21 75 15 13 10 Guaranteed Limit *55_C to 25_C v85_C 155 31 26 95 19 16 10 v125_C 190 38 32 110 22 19 10 Unit ns
ns
pF
9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (per Gate) (Note 10)
2f
24
pF
10. Used to determine the no-load dynamic power consumption: P D = CPD VCC Semiconductor High-Speed CMOS Data Book (DL129/D).
+ ICC VCC . For load considerations, see the ON
tr INPUT A OR B Y tTHL 90% 50% 10% tPHL 90% 50% 10%
tf
TEST POINT VCC GND DEVICE UNDER TEST OUTPUT CL*
tPLH
tTLH
*Includes all probe and jig capacitance
Figure 3. Switching Waveforms
Figure 4. Test Circuit
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74HC132
VT, TYPICAL INPUT THRESHOLD VOLTAGE (VOLTS) 4
3
VHtyp
2
1
2
3 4 5 VCC, POWER SUPPLY VOLTAGE (VOLTS) VHtyp = (VT + typ) - (VT - typ)
6
Figure 5. Typical Input Threshold, VT+, VT- Versus Power Supply Voltage
VH VIN
VCC VT + VT - GND VOH VIN
VH
VCC VT + VT - GND VOH
VOUT VOL VCC
VOUT VOL
(a) A SCHMITT TRIGGER SQUARES UP INPUTS (a) WITH SLOW RISE AND FALL TIMES
VIN
VOUT (b) A SCHMITT TRIGGER OFFERS MAXIMUM NOISE IMMUNITY
Figure 6. Typical Schmitt-Trigger Applications
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74HC132
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE H
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C -T-
SEATING PLANE
R X 45 _
F
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04 1 0.58
14X
14X
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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74HC132
PACKAGE DIMENSIONS
TSSOP-14 CASE 948G-01 ISSUE B
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V N
S
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K
0.15 (0.006) T U
S
J J1
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
0.36
14X
14X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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CCC EEE CCC EEE CCC
A -V-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
K1
DIM A B C D F G H J J1 K K1 L M
0.65 PITCH
DIMENSIONS: MILLIMETERS
74HC132
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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74HC132/D

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